OS Chapter 8

2015-11-01 17:18:43   0  举报

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AI智能生成

操作系统的第八章主要探讨了进程管理。这包括进程的创建、调度和终止，以及进程间的同步与通信。进程是计算机中进行计算的基本单位，它们可以并行执行以提高系统的效率。进程管理的目标是确保系统中的所有进程都能有效地共享处理器和其他资源。为了实现这一目标，操作系统需要对进程进行调度，决定哪个进程何时使用处理器。此外，进程间可能需要进行同步或通信，例如一个进程可能需要等待另一个进程完成其工作。在这一章中，我们还会讨论一些常见的进程调度算法，如先来先服务、短作业优先和优先级调度等。

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Background

Main memory and registers are only storage CPU can access directly Register access in one CPU clock (or less) Main memory can take many cycles Cache sits between main memory and CPU registers Protection of memory required to ensure correct operation

Address binding of instructions and data to memory addresses can happen at three different stages

Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes

Load time: Must generate relocatable code if memory location is not known at compile time

Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another

Logical vs. Physical Address Space

Logical address

Logical address – generated by the CPU; also referred to as virtual address

Logical address space is the set of all logical addresses generated by a program

Physical address

Physical address – address seen by the memory unit

Physical address space is the set of all physical addresses generated by a program

Logical and physical addresses are

the same in compile-time and load-time address-binding schemes;

differ in execution-time address-binding scheme

Memory-Management Unit (MMU)

Hardware device that at run time maps virtual to physical address

To start, consider simple scheme where the value in the relocation register is added to every address generated by a user process at the time it is sent to memory Base register now called relocation register

The user program deals with logical addresses; it never sees the real physical addresses

Dynamic Loading

Routine is not loaded until it is called

Better memory-space utilization; unused routine is never loaded

All routines kept on disk in relocatable load format

Useful when large amounts of code are needed to handle infrequently occurring cases

No special support from the operating system is required Implemented through program design OS can help by providing libraries to implement dynamic loading

Dynamic Linking

Dynamic linking –linking postponed until execution time

Small piece of code, stub, used to locate the appropriate memory-resident library routine

Stub replaces itself with the address of the routine, and executes the routine

Operating system checks if routine is in processes’ memory address If not in address space, add to address space

Dynamic linking is particularly useful for libraries

System also known as shared libraries

Swapping

concept

A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution Total physical memory space of processpokemon920528es can exceed physical memory

Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped

Does the swapped out process need to swap back in to same physical addresses?

Depends on address binding method

Backing store

fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images

Roll out, roll in

swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed

Context Switch Time including Swapping

If next processes to be put on CPU is not in memory, need to swap out a process and swap in target process

Context switch time can then be very high

100MB process swapping to hard disk with transfer rate of 50MB/sec

Plus disk latency of 8 ms Swap out time of 2008 ms (2000ms+ 8ms) Plus swap in of same sized process Total context switch swapping component time of 4016ms (> 4 seconds)

Can reduce if reduce size of memory swapped – by knowing how much memory really being used

System calls to inform OS of memory use via request memory and release memory

Contiguous Memory Allocation

Main memory usually into two partitions

Resident operating system, usually held in low memory with interrupt vector

User processes then held in high memory

Each process contained in single contiguous section of memory

memory mapping and protection

Relocation registers used to protect user processes from each other, and from changing operating-system code and data

Base register contains value of smallest physical address

Limit register contains range of logical addresses – each logical address must be less than the limit register

MMU maps logical address dynamically

Can then allow actions such as kernel code being transient and kernel changing size

Multiple-partition allocation

Hole – block of available memory; holes of various size are scattered throughout memory

When a process arrives, it is allocated memory from a hole large enough to accommodate it

Process exiting frees its partition, adjacent free partitions combined

Operating system maintains information about: a) allocated partitions b) free partitions (hole)

How to satisfy a request of size n from a list of free holes?

First-fit: Allocate the first hole that is big enough

Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size

Produces the smallest leftover hole

Worst-fit: Allocate the largest hole; must also search entire list

Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage utilization

Fragmentation

External Fragmentation

total memory space exists to satisfy a request, but it is not contiguous

Internal Fragmentation

allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used

Reduce external fragmentation by compaction

Shuffle memory contents to place all free memory together in one large block

Compaction is possible only if relocation is dynamic, and is done at execution time

I/O problem

Latch job in memory while it is involved in I/O Do I/O only into OS buffers

Paging

concept

Its a memory-management scheme that permits the Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available

Divide physical memory into fixed-sized blocks called frames Size is power of 2, between 512 bytes and 16 Mbytes

Divide logical memory into blocks of same size called pages

To run a program of size N pages, need to find N free frames and load program

Set up a page table to translate logical to physical addresses

Backing store likewise split into pages

disadvantage : Still have Internal fragmentation

Address Translation Scheme

Page number (p) – used as an index into a page table which contains base address of each page in physical memory

Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit

Calculating internal fragmentation

Page size = 2,048 bytes Process size = 72,766 bytes 35 pages + 1,086 bytes Internal fragmentation of 2,048 - 1,086 = 962 bytes Worst case fragmentation = 1 frame – 1 byte On average fragmentation = 1 / 2 frame size So small frame sizes desirable? But each page table entry takes memory to track Page sizes growing over time

Implementation of Page Table

Page table is kept in main memory

Page-table base register (PTBR) points to the page table

Page-table length register (PTLR) indicates size of the page table

In this scheme every data/instruction access requires two memory accesses

One for the page table and one for the data / instruction

The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs)

Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process

On a TLB miss, value is loaded into the TLB for faster access next time

Replacement policies must be considered

Some entries can be wired down for permanent fast access

Associative Memory

Associative memory – parallel search

Address translation (p, d) If p is in associative register, get frame # out Otherwise get frame # from page table in memory

Effective Access Time

Associative Lookup = "e" time unit Can be < 10% of memory access time

Hit ratio = "a" Hit ratio – percentage of times that a page number is found in the associative registers; ratio related to number of associative registers

Consider "a" = 80%, "e" = 20ns for TLB search, 100ns for memory access EAT = 0.80 x (20 + 100) + 0.20 x (20 + 100 + 100) = 140ns

Consider slower memory but better hit ratio -> "a" = 98%, "e" = 20ns for TLB search, 140ns for memory access EAT = 0.98 x 160 + 0.02 x 300 = 162.8ns

Memory Protection

Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed Can also add more bits to indicate page execute-only, and so on

Valid-invalid bit attached to each entry in the page table: “valid” indicates that the associated page is in the process's logical address space, and is thus a legal page “invalid” indicates that the page is not in the process’ logical address space Or use PTLR (Page-table length register)

Shared Pages

Shared code

One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems)

Similar to multiple threads sharing the same process space

Private code and data

Each process keeps a separate copy of the code and data

The pages for the private code and data can appear anywhere in the logical address space

Structure of the Page Table

concept

Memory structures for paging can get huge using straight-forward methods Consider a 32-bit logical address space as on modern computers Page size of 4 KB (212) Page table would have 1 million entries (232 / 212) If each entry is 4 bytes -> 4 MB of physical address space / memory for page table alone Don’t want to allocate that contiguously in main memory

Hierarchical Paging

Break up the logical address space into multiple page tables A simple technique is a two-level page table We then page the page table

Two-Level Paging Example

A logical address (on 32-bit machine with 1K page size) is divided into: a page number consisting of 22 bits a page offset consisting of 10 bits Since the page table is paged, the page number is further divided into: a 12-bit page number a 10-bit page offset Thus, a logical address is as follows:where p1 is an index into the outer page table, and p2 is the displacement within the page of the inner page table Known as forward-mapped page table

Hashed Page Tables

Common in address spaces > 32 bits

The virtual page number is hashed into a page table This page table contains a chain of elements hashing to the same location

Each element contains

(1) the virtual page number

(2) the value of the mapped page frame

(3) a pointer to the next element

Virtual page numbers are compared in this chain searching for a match If a match is found, the corresponding physical frame is extracted

Inverted Page Tables

One entry for each real page of memory

Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page

Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs