Rocket Chip
2017-09-04 14:40:07 0 举报AI智能生成
rocket 核代码总览 逐步更新
作者其他创作
大纲/内容
rocket.scala
HasCoreParameters
Rocket(core)
io
interrupts
hartid
imem->L1I
dmem->L1D
ptw
fpu
RoCCInterface
cmd:RoCCCommand
resp:RoCCResponse
mem:HellaCacheIO
<busy
<interrupt
optional
autl:UncachedTileLinkIO
utl:RoccNMemChannels|UncachedTileLinkIO
ptw:RoccNPTWPorts|TLBPTWIO
fpu_req/fpu_resp
>exception
decode_table->idecode.scala->instructions.scala
IDecode(64)
SDecode
DebugDecode
MDecode(64)
ADecode(64)
FDecode(64)
DDecode(64)
RoCCDecode
Pipelined Control
ex/mem/wb IntCtrlSigs ->idecode.scala
ex/mem/wb/take reg
pipeline
decode
ibuf ibuf.scala
imem
kill
<-take_pc
<-take_pc_mem_wb || take_pc_id
take_pc_id :=FastJAL & !ctrl_killd & jal
pc
btb_resp
Branch Target Buffer->btb.scala
inst
id_expanded_inst
id_inst
decode->id_ctrl
raddr: rs3/rs2/rs1
waddr: rd
csr
-> csr.scala
stall for fence
AMO(Atomic Memory Operation)
bpu
BreakpointUnit->breakpoint.scala
exception
id_xcpt_if
id_xcpt
id_xcpt_cause
dcache_bypass_data
detect bypass opportunities
bypass_source
execute
bypass_mux
ex_op1/ex_op2
alu
dpath_alu.scala:ALU
>dw
>fn
>in1/2
<out
<adder_out
<cmp_out
div
multiplier.scala:MulDiv
req
FN_DIV
FN_REM
FN_DIVU
FN_REMU
FN_MUL
FN_MULH
FN_MULHU
FN_MULHSU
in1/2
tag
ex_waddr
valid
ex_reg_valid = ! ctrl_killed
ex_ctrl.div
resp
data
>kill
kill/replay/valid/interrupt/ctrl
memory
todo
write back
wb_reg_valid = !ctrl_killm
wb_reg_replay ?
wb_reg_xcpt
wb_reg_wdata=fpu.data/mem.data
wb_set_sboard= div/dcache_miss/rocc
writeback arbitration
rf.write
hook up control/status regfile
stall
RAW/WAW execute
id_ex_hazard
ex_cannot_bypass
csr | jalr | mem | div | fp | rocc
data_hazard_ex
wxd & chechHazards
fp_data_hazard
RAW/WAW memory
id_mem_hazard
mem_cannot_bypass
csr | mem&mem_mem_cmd_bh | div | fp | rocc
mem_mem_cmd_bh
fastLoadWord
fastLoadByte
mem_reg_slow_bypass
data_hazard_mem
wxd & checkHazards
RAW/WAW write back
id_wb_hazard
data_hazard_wb
wb_set_sboard
ctrl_killd
ctrl_stalld
id_sboard_hazard/id_ex_hazard/id_mem_hazard/id_wb_hazard
id_ctrl.fp & id_stall_fpu
id_ctrl.mem & dcache_blocked
id_ctrl.rocc & rocc_blocked
id_ctrl.div & (!(div.io.req.ready || (div.io.resp.valid && !wb_wxd)) || div.io.req.valid)
id_do_fence
csr.io.csr_stall
! ibuf.inst.valid
ibuf.inst.replay
take_pc_mem_wb
csr.interrupt
CommitLog
functions
checkExceptions
PriorityMux
checkHazards
apply
with hazard_target
with fp_hazard_target
encodeVirtualAddress
scoreboard: one bit for one reg
fp_board
sboard
function
set one reg to 1
clear one reg to 0
read one reg
readBypassed: not used
ImmGenInstruction->Imm
RegFile31+0
收藏
收藏
0 条评论
回复 删除
下一页
