rocket-core

fpu

imem

dcache_blocked-ctrl_stalld

id_ctrl

CSR

csr.io.rw.rdata

2/4 (JAL)

wb_valid

id_xcpt/cause

checkexception

rf_addrMux by llwen

bypass_mux

!dmem.resp.valid

dmem

mem_reg_btb_resp/hit

mem_reg_pc/inst

wb_ctrl.wxd

mem&!dem.req.ready

ex_reg_pc

WB:dmem_resp_...

rf.write

resp.data

rf_wdata

IO bundle

ex_op1Mux by ex_ctl.sel_alu1

id_waddr

take_pc_mem_wb

mem_xcpt/cause

Branch Target Buffer- btb.scala

id_reg_fence=F

ex_reg_valid

valid

csr.io.csr_stall

id_bypass_src

jalr

wb_reg_replay

replay_wb_common

mem_reg_rs2

rfRegFile

ctrl_killd

id_ctrl.mem & dcache_blocked

ex_reg_rs_lsb/msb

take_pc_wb

ex_op2Mux by ex_ctl.sel_alu2

Stall & Kill & Replay & Exception

take npc in id

wb_set_sboard

ex_reg_xcpt/cause

IO

ID

flush_tlb

mem_br_taken

replay_wb_rocc

EX

hartid

ll_waddr

wb_reg_valid &wb_ctrl.fence_i &!dmem.s2_nack

id_expanded_inst

nack_mem

inst

wxd

killm

ex_load_use

wb_waddr

ptbr/status

csr.evec//exception or [m|s]retwb_reg_pc//replaymem_npc// branch mispredictid_npc//JAL

id_raddr2

replay_ex_structural

fp

WB

module

wb_reg_rs2

sboard.set

id_illegal_insn(check illegal)/id_expt_if/csr.interrupt/bpu.debug_if/bpu.xcpt_if

s2_nack

fastJAL(config)!ctrl_killdid_ctrl.jal

!valid||replay

ex_imm

mem_misprediction

fence_i

mem_reg_xpt_interrupt

!resp.valid

ex_reg_btb_resp/hit

fpu_kill_mem

FPU

cmd.rs2

rocc

req.valid

mem_wrong_npc

wb_wxd

ll_wdata

ex_reg_replay

id_csr_flush

mem_cfi_taken:branch&take|jalr|jal

rf_wen

div&!div.req.ready

id_do_fence: todo amo/fence etc.

id_raddr3

resp.ready

sboard

id_rs

wb_reg_xcpt/cause

resp

fp_sboard

take_pc

ex_reg_flush_pipe

control/Bool

pc

id_load_use

replay_ex_load_use

I1I Cache

mem

btb_resp

wb_dache_miss

kill

mem_reg_wdata

dmem.resp.bits.data

dw/fn

mem_npc

I1D Cache

resp.data_word_bypass/typ

ptw

id_npc (for jal)

flush_icache

id_ctrl.fp & id_stall_fpu

id_ex/mem/wb_hazard

ex_reg_pc/inst

mem_int_wdata

wb_reg_wdata

todo:CSR

mem_ctrl

div

Todo:id_csr...id_amo...id_fence

tag=ex_waddr

take_pc_id

fatc

alu

replay_next

ex_reg_xcpt_interrupt

ctrl_killx

mem_reg_flush_pipe

ctrl_stalld

id_ctrl.div & *div_blocked

ex_pc_valid

id_inst

Exceptions：*************************************id_xcpt:--------------------------------------csr.interruptbpu.debug_ifbpu.xcpt_ifid_xcpt_if(page fault)id_illegal_insn--------------------------------------ex_xcpt:--------------------------------------ex_reg_...fpu.illegal_rm--------------------------------------mem_xcpt:--------------------------------------mem_reg_...mem_new_xcpt--------------------------------------mem_new_xcpt:--------------------------------------mem_debug_breakpointmem_breakpointmem_npc_misaligned(fetch)dmem.xcpt.ma.st(misaligned_store)dmem.xcpt.ma.ld(misaligned_load)dmem.xcpt.pf.st(fault_store)dmem.xcpt.pf.ld(gault_load)--------------------------------------

wb_dcache_miss

mux by lsb

store_data

ibuf-ibuf.scala

wb_wen

val Bool

invalidate

bht_update

wb_reg_valid

EX:ctrl/tag/alu.out

bypass_sources

ras_update

!take_pc_wb

ex_xcpt/cause

= (in source)

cmd.ready

killm_common

ras_update.retrunAddr

sdata(last cycle)

mem_br_target:pc+Imm(ctrl.branch)/pc+Imm(!fastJAL&jal)/pc+2(mem_reg_rvc)

status/bp

BPU

wb_ctrl.rocc/div

!jalr

id_ctrl.rocc & rocc_blocked

resp.rd

:= (in source)

mem_reg_xcpt/cause

todo:2-cycle load-use delay for LB/LH/SC

!

mem_reg_load/store

new_reg_xcpt/cause

replay_ex

ex/mem/wb_addr

id_sboard_hazard

mem_cfi:branch|jalr|jal

btb_update

interrupts

mem_reg_replay

ea

ROCC

req.speculative

take npc in mem/wb

ibuf.pc

req.ready + req.valid

ex_ctrl

req.pc

id_raddr1

replay_mem

!ctrl_killd& id_ctrl.fp

dcache_kill_mem

decode- idecode.scala

bht_update.isValid

sboard.clear

wb_xcpt

bht_update.mispredict

normal

mem_reg_valid

cmd.ready + cmd.valid

MEM

replay_wb

IF

ex_rs(2)

bypass

csr.interrupt

ll_wen

killx

req.tag/cmd/typ

ctrl_killm

dmem_resp_data/type

valid&pc

ImmGen(ex_ctrl)

wb_ctrl