CPU
2021-05-19 10:48:48 0 举报CPU数据通路图汇总
作者其他创作
大纲/内容
cause
MUL_DIV
rs
Address
IMEM[16:0]
CLK
MUX5
4
IMEM[15:0]
LO
addr
aluc[3:0]
IMEM[25:0]||00
EXT5
A
ALU
rt
ADD
B
MUX4
DMEM
31
EXT26
MUX3
c
IMEM[15:0]||00
NPC(ADD)
CP0
Regfile
DM_CS
CP0_data
MUX1
data
n
NPC+EXT18
PC[31:28]
MUX2
IMEM
z
exc_addr
rd
HI
CLZ
o
PC+4
DM_W
EXT18
DM_R
EXT16
PC
pc
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