Integration test
2019-07-25 10:05:55 0 举报AI智能生成
车载电子集成测试项目
作者其他创作
大纲/内容
Contract verification test
consumer-driven contract test
development of producer is done with consunmer-driven test suite
provider test
e.g public facing API
Non-regular intergration tests
safety measure verification tests
Watchdog verification
RAM test working ROM test working
NVRAM CRC working NVRAM consistency
security measure verification tests
Exceptional state/behaviour tests
bus overload / bus drop-out
overvoltage / undervoltage behaviour
Non integration test
Diagnostics verification
Service completeness
XCP workability
Kostia Verification
Bus tests
NM working
Bus conformance tests
Robustness tests
Aging/abrasion tests
Dynamic Test
Resource(Dynamic)
Stack load
peak/worst case
intended stack overflow test
check the "stack check"
NVRAM access Frequency check eg.counter
Performance
CPU load/task time/ interrupt time/latency/dropouts/average load/peak load worst case
give limites, use of automated limit checks
heavy load scenarios I/O load (regular frequency,clipping freq)
start timeing shutdown /sleep timing
chain of event analusis(latency,tolerance )
Static Analysis
QAC/ Polyspace
Resource(Static)
Module RAM usage
Module ROM usage
NVRAM usage/lifetime calculation
Prongram architecture
All moudles integrated/check moudles version
interface compatibiliy/warning
RTE connection warnings
Quick check/acceptance test
Basic operation tets
simple bus operation
Basic fucntional test
simple action
simple measurement
Basic customer diagnostics test
Login ident
Basic Kostia test
login read memory
Long-term/continus running
Sleep/Wake cucle tests
CAN node wakeup
local wake up reason
NVRAM interruption test
Reset tests
NVRAM interruption test
Flashing test/bootloader
动作
production sequence simulation test
SW/HW configuration verification test
SPI
baudrate
parity
timing
MCU
controller setup
clock configuration
PLL start
PORT
Port/pin configrtion
Other peripherals
HSI depentdent
other MCAL
CAN/LIN
ADC
PWM
ICU
Specials
SW configuration verification test
Verification
COM signal access verification
NVM block access verification
OS runnable allocation verification
OS configuration verification
e.g paired interrupts locking
I/O signal access verification
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