Hwan's cpu
2020-10-23 22:41:20 0 举报cs
作者其他创作
大纲/内容
01
(DR1)+(DR2)->BUS->AR
55
31
20
33
2E
(DR1)∨(DR2)->BUS->Rd
RAM->BUSBUS->DR2
(Rs)->BUSBUS->DR1
K T
RAM->BUSBUS->DR1
RAM->BUS->Rd
10
x=01
0A
0E
(DR1)>BUSBUS->PC
(DR1)∨(DR2)+(DR1)∧(~DR2)->BUS->Rd
0C
03
36
1C
2F
(PC)->AR
SUB
(DR1)∧(DR2)->BUS->Rd
(Rd)->BUSBUS->DR2
38
TJ
P(1)
(SW)->BUSBUS->IR
00
16
1F
(SW)->BUSBUS->DR1
02
RM(10)
WM(11)
56
1A
14
23
(Rd)->BUSBUS->RAM
RAR
STA
RAM->BUS->DR1(PC)+1
(Rd)->BUS
1B
LDI
07
30
09
24
35
11
60
32
21
(PC)->BUSBUS->DR2
RAL
(PC)->AR(PC)+1
(DR1)->BUS->Rd
(DR1)+(DR2)->BUS->Rd
04
27
(DR1)∨(~DR2)+(DR1)->BUS->Rd
62
1/2(Rd)->Rd
2D
MOV
34
(R2)->DR2
17
25
0F
28
x=10
63
(DR1)>BUSBUS->RAM(PC)+1
X=00
12
RAM->BUSBUS->Rd
RAM->BUSBUS->IR
06
(Rd)->BUSBUS->DR1
~(DR1)->BUS->Rd
1E
19
ADD
(PC)->AR(PC)+1>PC
0B
2B
LAD
15
1D
JMP
18
29
13
05
OR
COM
CAL1
(DR2)->BUSBUS->PC
AND
2A
x=11
(SW)->BUSBUS->PC
P(4)
NOP
HLT
(DR2)->BUSBUS->AR
2C
JC
P(2)
P(3)
2*(Rd)->Rd
(DR1)-(DR2)->BUS->Rd
0D
08
QD(00)
(DR2)>BUSBUS->AR
22
CAL2
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