FPGA DDR3 AXI4
2021-01-27 19:12:53 0 举报FPGA DDR3 控制器 MIG AXI4 接口需要使用的信号
作者其他创作
大纲/内容
axi_arprot [3bit]
axi_araddr [27bit]
灰色的信号用不到
AXI MasterCtrl
axi_awqos [4bit]
axi_arburst [2bit]
axi_wdata[32bit]
axi_awready
axi_bresp [2bit]
axi_rdata [32bit]
axi_rresp [2bit]
axi_rid [4bit]
Interface Write Address Ports
axi_rlast
axi_arvalid
axi_bready
axi_awaddr [27bit]
axi_rready
axi_arcache [4bit]
MIG
axi_awsize [3bit]
Interface Read Data Ports
axi_awcache [4bit]
axi_arqos [4bit]
axi_awlock
axi_awburst [2bit]
axi_rvalid
axi_arlen [8bit]
axi_wvalid
axi_wlast
axi_bid [4bit]
axi_awlen [8bit]
Interface Read Address Ports
axi_wstrb [4bit]
axi_awvalid
axi_arlock
axi_arid [4bit]
axi_wready
Interface Write Data Ports
Interface Write Response Ports
axi_awid [4bit]
axi_bvalid
axi_arready
axi_awprot [3bit]
axi_arsize [3bit]
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