单周期处理器数据通路
2021-12-21 21:08:09 43 举报单周期处理器数据通路
作者其他创作
大纲/内容
ALU result
Instruction[31:0]
0
MemRead
b
writedata
Zero
Register
4
mux4
A
ALUcontorl
mux1
control
write register
ALU
Readregister 2
1
ALUSrc
Instruction
32
shift left 1
Instruction[6:0]
Branch
readdata 2
memtoreg
Readaddress
PC
readdata 1
Regwrite
a
Writedata
DataMemory
InstructionMemory
Instruction[11:7]
Memwrite
&
Instruction[19-15]
64
>=1
j
Readregister 1
mux2
mux3
ADD
ImmGen
Instruction[24:20]
Aluop
Address
B
Readdata
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