数字存储示波器结构框图
2023-03-06 16:08:07 0 举报数字存储示波器结构框图
作者其他创作
大纲/内容
DAC
Data Accelerator
TimeBase(OCOX)
采样
Duplicator
External Trigger
Data Accuisition
Clock Sample
Edge Trigger
ADC
Sample and Hold S/H
Address Counter
Attenuator
Data Display
Horizonal Amplifer
Analog Trigger
Memory
V1
HW Serial Trigger
Sampler
CRT
Input Signal
Amplifer
Control Circuits
Pre-Amp
Internal Trigger
PICe to CPU
Vertical Amplifer
Probe
TimeBase Counter
V2
Buffer
收藏
职业：暂无
0 条评论
下一页
